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Fabricating Semiconductor Lines on a Narrower Than Conventional Pitch Disclosure Number: IPCOM000057468D
Original Publication Date: 1988-May-01
Included in the Prior Art Database: 2005-Feb-15

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Related People

Cronin, JE Holland, KL Lee, PP [+details]


A technique is described for fabricating semiconductor lines with a narrower than conventional pitch using a single chemical vapor deposition (CVD) metal and two masking steps. As semiconductor dimensions shrink, line capacitance and resistance increase by at least the factor of the shrink. High leverage wiring techniques provide the technology for shrinking dimensions, as well. Metal line pitch, line-to-line capacitance and line resistance can be reduced by placing one line in an insulator trough and another on the insulator surface, as shown in the figure. The two lines can be a minimum dimension in width, but the separation is the overlay tolerance rather than the minimum image spacing.