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Maximizing Direct Memory Access Efficiency in Multi-Master Bus Systems

IP.com Disclosure Number: IPCOM000057475D
Original Publication Date: 1988-May-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Keener, DS [+details]

Abstract

This article describes a technique in multi-master bus systems in which a direct memory access (DMA) arbitration results in a larger data transfer, thereby reducing the total amount of arbitrations that must occur to pass a given data block. In a multi-mastered bus system DMA transfers are accomplished by a device arbitrating for the bus and, upon winning the arbitration, transferring the data. The arbitration time is overhead on the transfer time since no data is transferred during this time. Therefore, if the amount of time to transfer one byte is equivalent to the time for arbitration, then one-byte transfer is fifty percent efficient. If the arbitration resulted in three data byte transfers, then the transfer is seventy-five percent efficient.