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Reference Voltage and Bias Circuits for Magnetic Recording Channels Integrated in CMOS Technology

IP.com Disclosure Number: IPCOM000057481D
Original Publication Date: 1988-May-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
De La Moneda, F Hohl, TH [+details]

Abstract

In this article we describe reference voltage and bias circuits for magnetic recording channels. The novel concepts underlying these circuits are intimately related to the design in CMOS technology. Fig. 1 shows the block diagram of the read channel up to the input of the peak detector circuit. The functions of the blocks are the same as in presently used recording channels; only the implementations are different. The circuit to be disclosed here is represented by the block at the lower right. (Image Omitted) The circuit diagram for the circuit represented by the block "reference voltage and bias circuits" is shown in Fig. 2. The circuit is to generate all DC bias voltages for the automatic gain control (AGC) circuits. It receives no input voltage.