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Dual Processor Implementation for Pc-Based 370 Microprocessors

IP.com Disclosure Number: IPCOM000057484D
Original Publication Date: 1988-May-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Hunt, GD [+details]

Abstract

Two IBM 370 processor cards which run simultaneously in a personal computer can communicate as dual processors when implemented in the following manner. Each processor card has the global architecture shown in Fig. 1. Each processor card 1 has memory 2, a memory start address register 3 (set by microcode), and control registers 4. A P1/P2 (Processor identification) switch 5 sets the default switch process or number. The (Image Omitted) switch 5 also controls the default address for the processor card control registers. The P1/P2 switch can be overridden by microcode. The processor cards have external pins for the address/data bus, and the cards are cabled together. This allows the necessary control information to be sent from card to card. Memory access will be controlled by a synchronization clock.