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On-Chip Logic Enhancements for Test of Error Checking and Correcting Related Functions in On-Card Applications

IP.com Disclosure Number: IPCOM000057490D
Original Publication Date: 1988-May-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Arlington, DL Evans, EK Hansen, RC Rogers, JF [+details]

Abstract

Testing of error checking and correcting (ECC) and extended ECC operations at the chip or module level is relatively simple before the module(s) are soldered on card. After soldering, external control of key module input/outputs is no longer possible. The logic enhancements described in the following are a means of addressing this problem. In order to check that on-chip ECC is working, inputs to the ECC encode and/or syndrome circuitry must be easily alterable. In many applications, these inputs are data and check bits from memory arrays. The problem encountered with some cards is that the ECC logic and the arrays are both on the same card. In many memory card applications the ECC logic is elsewhere in the system, and thus the memory/ECC interface is across an available external bus.