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Optimum Routing of Critical Circuit Timing Paths Disclosure Number: IPCOM000057505D
Original Publication Date: 1988-May-01
Included in the Prior Art Database: 2005-Feb-15

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Davis, JW Glenn, RD Lleonart, G [+details]


A technique is described herein to prevent timing and performance problems and reduced power dissipation in VLSI circuit design. The technique consists of identifying critical circuit nets, reducing critical net lengths, and optimally routing critical nets. The driver size is also optimized according to net length. The key advantage of this method is its fully automated nature. The software automatically finds the critical nets and provides the best possible performance along with the minimum power dissipation. A related benefit is that the procedure is designed to be part of a "top down" hierarchical design system, and it is easily implemented in large circuit chips where manual procedures are extremely cumbersome. The size of driver circuits is also optimized according to the length of the nets.