Original Publication Date: 1988-May-01
Included in the Prior Art Database: 2005-Feb-15
In a high performance pipelined machine with instruction buffers, a branch history table, and a large cache close to the instruction unit and execution unit, a small least-recently-used (LRU) managed cache is provided for instructions that are targets of taken branches which were incorrectly guessed. The small cache (BWG - branch wrong guess) improves performance when the same branch is once again taken by providing the proper target without the two or more BWG cycle delay typically incurred. In a high performance pipeline machine with a large cache close to the instruction unit (I-unit) and execution unit (E-unit), a major problem is supplying instructions to the I-unit. Thus it is desirable for these machines to have several large instruction buffers (I-buffers).