Original Publication Date: 1988-May-01
Included in the Prior Art Database: 2005-Feb-15
Disclosed is an input-driven inverter which provides a push/pull output logic gate capable of operating at a 1.7-volt power supply level. The low power supply voltage is desirable to reduce on-chip power dissipation while the push/pull feature provides for low sensitivity to load capacitance. The disclosed circuit which provides high speed, low power and low cost logic, may be implemented in a bipolar/CMOS masterslice process technology. It utilizes field-effect transistor (FET) devices as substitutes for Schottky barrier diode (SBD) devices usually unavailable in many bipolar/CMOS technologies. The input driven inverter receives its base drive for the PNP and NPN bipolar inverters (transistors T1 and T2) from the driving stage or stages.