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Method for Testing Internal Tri-State Bus

IP.com Disclosure Number: IPCOM000057575D
Original Publication Date: 1988-Jun-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Leblanc, JJ Storey, TM [+details]

Abstract

A test method is shown for detecting tri-state bus faults for CMOS circuits. Testing internal logic bussing driven by CMOS tri-state drivers with dot ORed outputs can be difficult. Testing is not a problem if the dotted bus is at a logical 1 or 0 state; however, the neutral or high impedance state is a problem because present test generators cannot handle this condition, thus leaving a significant portion of such logic untested. The figure shows a dot ORed output 10 of two tri-state drivers 11 and 12. A dot OR is considered to be the physical connection of two or more circuit outputs. At the multichip package level, the state of node 10 may not be directly measurable. It may be necessary to determine the state of node 10 by driving the test into the shift register latch (SRL) 13 and scanning the SRL out.