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Shift Ring Using Two-Point Clock

IP.com Disclosure Number: IPCOM000057583D
Original Publication Date: 1988-Jun-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Westcott, GR [+details]

Abstract

A decodable shift ring, easily assembled of edge-triggered flip-flops in transistor-transistor logic (TTL), can also be constructed of set/reset and polarity hold latches and two point clock that are readily adapted to large-scale integration with its attendant requirements of single clock pulse resolution and alternating clock signals for level sensitive scan design. (Image Omitted) Referring to Fig. 1, a plurality of control signals (DEN, Task Bus Request and Select) are combined at AND gate 1 with L1 of Task Ram Cycle set/reset latch 2 to condition Task Request Pending set/reset latch 3. At clock Tl, latch 3 turns on and is effective at gate 4 with the absence of 186 Select signal at inverter 5 to condition latch 2 via gate 6.