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Automatic Direct Memory Access Buffering in a Mixed-Width/Dual-Memory System Architecture Disclosure Number: IPCOM000057586D
Original Publication Date: 1988-Jun-01
Included in the Prior Art Database: 2005-Feb-15

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Riley, MW Upton, JD [+details]


A method is described for use in a system in which main memory is wider than most direct memory access (DMA) devices using it, which involves accumulating DMA data in a hardware buffer prior to the final transfer to or from memory. Fig. 1 shows a simplified diagram of the IBM RT-PC system hardware architecture. Devices that attach to the PC-AT I/O Channel may be either 8 bits or 16 bits wide. The majority of PC-AT I/O channel devices that use System DMA are 8 bits wide. Main Storage is 32 bits wide with Error Checking and Correction (ECC) logic.