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Reduction of the Number of Inverters in a Logic Circuit Disclosure Number: IPCOM000057596D
Original Publication Date: 1988-Jun-01
Included in the Prior Art Database: 2005-Feb-15

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Berman, CL Brand, D Joyner, WH Trevillyan, LH [+details]


A method is provided for optimizing the number and location of logic inverters in a logic circuit wherein at least the primitive functions of AND, OR, NAND, NOR and NOT are available.