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Dense ROM Architecture for Cmos Gate Arrays

IP.com Disclosure Number: IPCOM000057615D
Original Publication Date: 1988-Jun-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Coppens, P Denis, B Nicot, S [+details]

Abstract

The following describes a ROM architecture intended to be implemented as a macro on a gate array background. The major advantage is that this ROM macro can be personalized like standard gate array library books. It is generated automatically to a user-defined size (word lines and bit lines) as a growable macro. Device usage in the array has been maximally optimized as both P and N devices store data bits. Either a P or N device stores 1 bit of data by connection of its drain to a bit line and connection of its source to either GND or VDD (personalization at contact level). Excellent density is achieved by having a word going both horizontally and vertically along a word line (WL). Each WL is dedicated to a word decoder. Further decoding is done at sense amplifier level to accommodate "P" or "N" bit lines.