Verification of Error Correction Circuitry
Original Publication Date: 1988-Jun-01
Included in the Prior Art Database: 2005-Feb-15
The increasing integration of semiconductor memories and their error correction circuitry has led to problems in single and multiple bit error correction testing. Frequently, data bits involved in testing are no longer accessible outside the storage chip. This article describes how machine check actions can be verified by integrating a XOR gate and a comparator on the storage chip. In a normal mode, whenever a single bit error is detected in a read cycle, the illustrated error correction circuitry ECC corrects the failing bit. If correction has been successful, the corrected byte will be restored in the memory without the system receiving an error message. Depending upon the type of ECC used, multiple bit errors may be corrected.