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Zero Detection for Improved Multiplication Performance Disclosure Number: IPCOM000057686D
Original Publication Date: 1988-Jun-01
Included in the Prior Art Database: 2005-Feb-15

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Cocanougher, D Hicks, T Karim, F [+details]


This article describes a technique for increasing the speed of a 64-bit multiplier without sacrificing precision. As the working format of a processor increases from 16 bits to 32 bits, the capability of high performance floating point multipliers must increase from a maximum of a 32-bit double-word operation to a 64 bit. A floating point supporting both these formats of operands could (Image Omitted) sacrifice performance of the smaller operations for this flexibility in formats. The floating point unit multiplier disclosed herein performs a 64 bit fraction multiply, but a fraction of 15 significant bits does not require the same execution time as that of 55 bits. This floating point operates with the three IEEE standard binary formats shown in Fig. 1.