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62-Bit-Wide Arithmetic and Logic Unit Combining the CARRY LOOK AHEAD and CARRY SELECT ADDER Principles

IP.com Disclosure Number: IPCOM000057687D
Original Publication Date: 1988-Jun-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Proust, JM [+details]

Abstract

The speed of an arithmetic and logic unit (ALU) depends on the number of bits it has to handle. In a classic embodiment, the least significant bits are always available before the most significant bits. To get around this disadvantage, an improved ALU has to be designed so that the most significant bits are accelerated. Half-sum generates and propagates are formed for each pair of bits (left and right operands). Then the ALU is divided in three groups of sixteen bits, themselves being divided in four groups of 4 bits and a group of fourteen bits itself divided in two groups of four bits and a group of six bits. From the four- and six-bit groups are formed the first level generate and propagate groups (GG1 and GP1).