Browse Prior Art Database

Trinary Level Input Clock Generator

IP.com Disclosure Number: IPCOM000057693D
Original Publication Date: 1988-Jun-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Grimes, DW [+details]

Abstract

Using a trinary level input 0, 1, 2 and trinary logic, four binary clock times are generated. Referring to Fig. 1 and 2: When the input is at +VDD (+), the TRIT RCVR (+) output is 1. When the input is at Center (C), the TRIT RCVR (C) and (C-not) are 1 and 0, respectively. When the input is at at Ground (-), the TRIT RCVR (-) output is 1. At the start of the timing diagram, the input is at Ground (-), and the TRIT RCVR (-) output is logic 1, which is amplified through Driver #2 (D2) to provide logic level 1 on the Clk 0 output when the input is (-). The Clk 0 output is the data input to the UP Latch, and TRIT RCVR output - is the clock input to the UP Latch. With the UP Latch Clock input being 1 and the Data input being 1, the UP Latch is set to the ON state, making Q = 1 and Q- = 0.