Latch Feedback Timing Analysis Enhancement
Original Publication Date: 1988-Jun-01
Included in the Prior Art Database: 2005-Feb-15
High level hardware description languages and associated "compilers" used in conjunction with "free running clocks" to LSSD SRLs cause false reports of timing problems. Manual intervention is low, inefficient, and results in errors requiring multiple timing runs. The compiler can detect the situations, using structural information it can derive from the high level description, and provide automatic relief from these false reports. High level hardware description languages, such as VHDL, may be "compiled" into hardware descriptions that may be converted into actual hardware. For example, VHDL could be compiled into IBM's BDL/S (Basic Design Language for Structure) and then transformed into a hardware design by IBM's EDS system.