Interrupt Pulse Mask Enable
Original Publication Date: 1988-Jun-01
Included in the Prior Art Database: 2005-Feb-15
This invention provides a means for software operating in a processor to enable the reception of interrupts to the processor interrupt hardware for a single instruction cycle. It is intended to reduce the amount of overhead incurred by software in handling the high volume of non-critical interrupts that occur during communication between multiple processors. Communication between multiple processors typically uses a large number of low-priority interrupts. The purpose of these interrupts is to inform the receiving processor of a request for service. Interrupts to a processor are controlled by external hardware that provides the ability to mask all or selected interrupts until the software is ready to work on the interrupt(s).