Channel Check Protocol-Error Detection/Correction Protocol
Original Publication Date: 1988-Jun-01
Included in the Prior Art Database: 2005-Feb-15
This article describes a channel check (CH CK) protocol in a processor which provides a technique for low-end workstations to detect and recover from bus exception conditions. Memory parity errors and correctable system errors are identified to the system processor (default channel master) by masters or slaves by means of the CH CK signal. This error indication is not an interrupt level, but is managed by the system processor as though it were the highest priority non-maskable system interrupt. The system processor and its system software is ultimately responsible for system recovery. When a master other than the system processor detects CH CK, it relinquishes control of the bus and the system processor handles the error recovery. The following table summarizes the address assignment of status and CH CK control.