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Virtual Floating Point Register Techniques

IP.com Disclosure Number: IPCOM000057739D
Original Publication Date: 1988-Jun-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Rodriguez, JR [+details]

Abstract

This article describes a technique whereby a copy of a portion of a large set of floating point (FP) data registers is kept in the FP registers inside the floating point unit (FPU) when the set is too large to be fully contained inside the FPU. (Image Omitted) Some FP architectures define arithmetic on operands that reside in a register involving multiple sets of registers, where each set can be assigned to one or more program processes. The emulation of this type of architecture with a FPU containing a single register set suffers from a resulting loss in performance due to the time it takes to do the transfers between the host processor's registers and the floating-point registers (FPRs) in the FPU. Disclosed herein is a technique used in the emulation of a host FP architecture with multiple data register set requirements.