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Early Read of Dynamic RAM in an Intel 80286 Microprocessor-Based System Disclosure Number: IPCOM000057755D
Original Publication Date: 1988-Jul-01
Included in the Prior Art Database: 2005-Feb-15

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Galella, JW Prais, MW [+details]


This article describes a technique utilizing early read of dynamic RAM (DRAM) in an Intel* 80286 microprocessor-based system to eliminate the need for additional wait states during memory reads which results in an increase in system performance. (Image Omitted) Referring to the timing diagram of Fig. 1 in 80286-based systems the typical memory access cycle is initiated by the memory read or write command signal (CMD). When considering memory reads, there is a delay associated with DRAM access time before data is considered valid. In addition to DRAM access time, there is also a delay associated with any error detection scheme used. Error correction code (ECC) can be used for this purpose. Data bus transceivers also add some delay from the time that the memory read begins to data is valid at the 80286.