Browse Prior Art Database

Simultaneous Precise Generation of Different FET Channel Lengths During the Sidewall Image Transfer Process

IP.com Disclosure Number: IPCOM000057759D
Original Publication Date: 1988-Jul-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Koblinger, O Kroell, K Trumpp, H [+details]

Abstract

This article describes how precisely defined polysilicon spacers of different widths may be generated by a proximity effect during the sidewall image transfer (SIT) process. For CMOS technology, for example, it is desirable that the effective channel lengths of the two complementary transistors are substantially the same. However, the different implanted ions (boron and arsenic) diffuse into the carrier material at different speeds, leading to electrical channels of different lengths at identical gate sizes. To avoid this, it must be possible to select different P- and N-FET channel lengths during the manufacture of the transistors.