Browse Prior Art Database

FIFO Arbitrator

IP.com Disclosure Number: IPCOM000057764D
Original Publication Date: 1988-Jul-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Miller, EW [+details]

Abstract

This article describes a FIFO (first-in, first-out) Arbitrator which dynamically establishes the sequence in which four Link Adapters (LAs) will access a single memory port interface. The four LAs operate asynchronously of each other and may request access to the memory at any time. The logical pieces that make up the FIFO Arbitrator are listed below: 1. Time Slice Input Buffer 2. Change Detection Logic 3. Read-In Counter 4. Queue Buffer Matrix 5. Read Out Counter and Step Logic 6. Priority Buffer and Reset Controls 7. Priority Logic 8. Arbitration Cycle Control Logic (Image Omitted) Each of these is described in detail in the following text. Time Slice Input Buffer This is a four-bit buffer register into which the Request line from each LA is sampled every 125 nanoseconds.