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Regulated Clock Staggering Disclosure Number: IPCOM000057765D
Original Publication Date: 1988-Jul-01
Included in the Prior Art Database: 2005-Feb-15

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Koetzle, G Ludwig, T Schettler, H Wagner, O [+details]


A circuit for regulated clock staggering is described which staggers the clocks as a function of the switching speed of the chips employed. In CMOS circuits, a problem arises as the simultaneous switching of many latches leads to a very high current surge, which, in turn, leads to noise voltage across the power line inductance. This so-called delta I or noise problem occurs only with fast switching chips having short delays and low resistivity transistors. For such chips, it is desirable to split the critical clock into n partial clocks separated by a few nanoseconds. Thus, the current surge, caused by the switching latches, is spread over several nanoseconds, which reduces the noise voltage considerably.