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Longitudinal Redundancy CHECK Checking of Instruction Flow

IP.com Disclosure Number: IPCOM000057774D
Original Publication Date: 1988-Jul-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Jones, GD Larsen, LD [+details]

Abstract

A conventional way of providing error checking for instructions being accessed by a processor is to add parity bits, typically one parity bit per byte, to each instruction. Adding parity bits has the effect of increasing the instruction word size and, hence, memory interfacing cost and complexity. A new approach to checking instructions is disclosed. A variety of Longitudinal Redundancy Check (LRC) is performed on blocks of instructions. This scheme incurs some instruction storage and performance overhead, but does not increase instruction word size. It will, however, require an assembler able to compute check sums and insert them in the instruction stream. The block diagram (Fig.