Programmable LSSD Clock Generator
Original Publication Date: 1988-Jul-01
Included in the Prior Art Database: 2005-Feb-15
A programmable clock generator is described, whose time characteristics (cycle time, pulse width and phase) are freely programmable and, thus, readily changeable. Fig. 1 shows the block diagram of the programmable clock generator, and Fig. 2 shows a pulse diagram. Each output signal slope of the clock generator is derived from the taps of an external delay line (not shown) which is fed by a hybrid oscillator (not shown). The taps are combined in two groups A and B. The taps of each group are connected through receivers and buffers 1 to a selector 2 which, controlled by the information of a program store 3, switches one of its input lines 4 to a clock splitter 5. The clock splitter supplies two non-overlapping pulses for cyclically shifting the information stored in a feedback shift register 6.