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MODULAR IMPLEMENTATION OF b-ADJACENT CODES

IP.com Disclosure Number: IPCOM000057779D
Original Publication Date: 1988-Jul-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Chen, CL [+details]

Abstract

The class of b-adjacent error correcting codes (ECCs) is suitable for protecting data from errors in memory arrays organized in b-bits per chip. The basic b-adjacent error correction scheme has been described in [*]. Described in this article is an implementation scheme that uses the same basic modules for two different b-adjacent error correcting codes. These codes can be applied to a memory that has subsystems of different data widths. (Image Omitted) Assume that two memory subsystems are organized in 4 bits per chip with respect to ECC words. Subsystem A has a data width of 8 bits and subsystem B has a data width of 16 bits. Let code A and code B be the ECCs for subsystem A and subsystem B, respectively. It is required that both codes are able to correct any combination of 4-bit errors generated from a chip failure.