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Computing Channel Output Vectors in a Self-Test Circuit Using a MATRIX Disclosure Number: IPCOM000057786D
Original Publication Date: 1988-Jul-01
Included in the Prior Art Database: 2005-Feb-15

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Barna, EM Gupta, VP Lapointe, MJ [+details]


Given a device using a self-test configuration (Fig. 1), it is desirable to be able to calculate channel output vectors given the contents of the PRPGS (LFSR and MISR), as well as the bit stream entering the MISR Quotient register for a series of patterns. The channel output vector is defined as the bit stream entering the MISR from the last SRL in the specified channel. There is one bit for each scan clock pair applied during the execution of a group of test patterns. Such information is needed in diagnostics of a failing self-test configuration. See "Chip-Level Self-Testing Circuit for High Density Circuits," IBM Technical Disclosure Bulletin 28, 4669-4675 (March 1986). A matrix representation is used to solve the problem.