Browse Prior Art Database

Test Pattern Generation for Memory

IP.com Disclosure Number: IPCOM000057791D
Original Publication Date: 1988-Jul-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Chen, CL [+details]

Abstract

In a bit-sliced memory, each bit of an n-bit memory word is stored in a different physical entity, e.g., an array chip. Assume that all physical entities fail independently, the errors in an n-bit word are independent. The problem addressed in this article is the generation of a test set that can provide the coverage of all possible t-errors in an n-bit memory word, where t is less than or equal to 3. A test set for an n-bit word consists of a set of n-bit binary patterns or vectors. A test matrix T of n columns can be used to represent the test patterns in the test set. The number of rows in T is the number of test patterns of the test set or the size of the test set. In memory testing, each of the test patterns in the test set is stored in and fetched from each memory location.