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Error Checking for an ALU With Logic and Arithmetic Operations

IP.com Disclosure Number: IPCOM000057794D
Original Publication Date: 1988-Jul-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Hallman, SA [+details]

Abstract

This error checker predicts the parity of an eight-function arithmetic logic unit (ALU) and provides 100% error detection. It is based on several techniques, described in [*]. (Image Omitted) The eight functions, common to most ALUs, are designed to pass through the adder logic, taking advantage of the adder checks and circuitry.