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Cmos-Ttl Protective Circuit

IP.com Disclosure Number: IPCOM000057833D
Original Publication Date: 1988-Jul-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Ludwig, T Pollman, K Schettler, H Wagner, O [+details]

Abstract

A circuit is proposed which allows using advanced submicron technology chips, preferably of the CMOS type, along with conventional micron technology chips, with both chip types being connected to a common bus. As the very thin gate oxide and the short channel of submicron transistors are incapable of withstanding the higher operating voltage of about 5 V of conventional chips, the most positive up-level (MPUL) being, for example, 5.5 V, a circuit scheme is required which allows the two chip types to communicate without destroying the more sensitive new chips whose most allowable up level (MAUL) of, say, 4 V, is much lower. The protective circuit, illustrated in the figure, typically includes resistor R and transistor T3. Transistors T4 to T8 serve as a specific gate voltage generator for T3.