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Processor With Supraconductive Packaging and Directly Bonded Chips

IP.com Disclosure Number: IPCOM000057847D
Original Publication Date: 1988-Jul-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Briska, M Faix, W Kaercher, R Mueller, K Schramm, W [+details]

Abstract

This article relates to a planar technological variant of the supraconductive wiring geometry described in the preceding article. The array of this variant is marked by extremely dense supraconductive Niob wiring overlaying a specially designed Si wiring wafer. The VLSI chips to be wired are connected by a Niob fanout to the Niob wiring. An example of the proposed array is schematically illustrated in the figure. As shown, there are low temperature regions I of, say, about 4K, and operating temperature regions II of, say, > 40K. Chips 1 on wafer 2, coated with an about 20-mm-thick SiO2 layer 3, are positioned such that they have an operating temperature of about 40 to 60 K which is between the temperatures of liquid nitrogen and liquid helium.