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Multiple Queued Condition Codes Disclosure Number: IPCOM000057858D
Original Publication Date: 1988-Jul-01
Included in the Prior Art Database: 2005-Feb-15

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Emma, PG Knight, JW Pomerene, JH Rechtschaffen, RN Sparacio, FJ [+details]


A technique is described whereby the results of multiple arithmetic, logic or comparison operations, that are used in subsequent conditional branches, are retained through the use of multiple queued condition codes, so as to increase the opportunity for parallelism. The concept is particularly useful in reduced instruction set computers (RISC); however, any heavily pipelined architecture that depends on advanced compiler technology for code generation would benefit from the concept. Typically, RISC make no interlocking provision to insure that the results of condition code (CC) setting operations or memory access operations are complete in their formulation before they are required for processing in the system.