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Arithmetic Logic Unit Ripple Carry Propagation Bypass Circuit

IP.com Disclosure Number: IPCOM000057883D
Original Publication Date: 1988-Jul-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Bechade, RA [+details]

Abstract

A set of carry shunts are added to an arithmetic logic unit (ALU) adder carry chain to reduce worst-case carry ripple paths and enhance ALU performance. The additional circuits utilize a minimum amount of area and reduce the power-performance product. (Image Omitted) The ripple carry characteristics of an ALU can be the gating factor in a processor's performance. To compensate for ripple carry delays, full carry look-ahead ALU designs have been implemented at the expense of chip area and power. A simple carry shunt or bypass circuit which does not add significantly to an ALU's area and power is disclosed. A 32-bit position carry chain layout for an ALU adder is shown in Fig. 1 with one of many possible carry bypass circuit organizations in parallel.