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Well Control Technique for Series Complementary Metal Oxide Silicon Devices Disclosure Number: IPCOM000057887D
Original Publication Date: 1988-Jul-01
Included in the Prior Art Database: 2005-Feb-15

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Gray, KS Morrish, JR [+details]


By pulsing well potential, source-to-substrate voltage effect on device threshold voltage (Vt) is significantly reduced in series complementary metal oxide silicon (CMOS) devices. In a dual-well CMOS technology, this technique can be used on both n-channel and p-channel devices since they are in their own wells. In an n-well CMOS technology, this technique can only be used on the p-channel devices. Series device performance is significantly improved by use of this method. The figure shows a p-channel device in an n-well CMOS technology with its electrical connections: gate G, source S, drain D and well W. A timing diagram is included in the figure to show proper pulsing of those connections to p-channel series devices. All connections start at a high device potential Vdd.