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Process for Vertical PNP Transistor

IP.com Disclosure Number: IPCOM000057906D
Original Publication Date: 1988-Jul-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Arienzo, M Issac, RD [+details]

Abstract

High performance vertical PNP transistors can be fabricated by substituting a p+ subcollector for the usual n+ subcollector to provide adequate current carrying capability. Assuming standard bipolar processing occurs through the formation of an n+ subcollector and epitaxial layer, the wafer 1 will have regions 2 and 3 designated n+ and n-, as shown in Fig. 1. Protective oxide/nitride layer 4 is deposited. Regions 5 where vertical PNP transistors are to be placed are defined and the epitaxial and n+ subcollectors are removed by reactive ion etching. An oxide or oxide/ nitride layer is conformally deposited and etched to leave isolation sidewall 6. Selective epitaxial growth within the recess is then used to form a layer suitable for a vertical PNP transistor.