Voltage Discharge Test Circuit
Original Publication Date: 1988-Jul-01
Included in the Prior Art Database: 2005-Feb-15
The article describes a circuit which can be used to discharge nodal voltages during testing of VLSI circuits and VLSI circuit packages. The test circuit can be activated by decreasing the power supply voltage to a level that falls within a specified region. The test circuit is also activated whenever the said node voltage significantly exceeds the power supply voltage level. During normal operation and with normal power supply voltage levels, the test circuit is dormant and does not affect the functional circuitry. Referring to the figure, the voltage discharge test circuit includes a voltage divider network consisting of N-channel FET devices T1 and T2. The drain electrode of device T1 is connected to the power supply voltage Vdd. The source electrode of device T2 is connected to ground potential.