Browse Prior Art Database

Enhanced Performance and Wireability Package Adapter

IP.com Disclosure Number: IPCOM000057925D
Original Publication Date: 1988-Jul-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Olson, LT [+details]

Abstract

Dense multi-level wiring applications on multi-chip modules, in which adjacent signal lines run parallel for long lengths, typically have high interlevel coupled noise. This noise can be significantly reduced in the following manner. Top level metal layer (M2) signal line connections between chips and module input/output (I/O) pins run parallel for long lengths. A similarly wired bottom level metal layer (M1) has signal line connections between chips and module I/O pins that run parallel to the signal lines of M2. The separation between these two metal levels consists of a polyimide dielectric 1 shown in the cross section view of a standard three level metal substrate (Fig. 1). Below the two levels of metal M1 and M2 there is a ground plane M0, embedded in a dielectric material 2, which serves to minimize signal noise.