Browse Prior Art Database

Video Memory Paging Mechanism

IP.com Disclosure Number: IPCOM000057928D
Original Publication Date: 1988-Jul-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Lee, WR McNeil, WL Parsons, DH Thompson, SP [+details]

Abstract

A technique is described whereby multiple display screens, or pages, in a video display, as used in personal computers, utilize a video memory array to attain additional functions. The multiple screens, or pages, of video memory are addressable and consume memory address space that is only one page long. Independence of the display page and the page being accessed by the controlling microprocessors is preserved. (Image Omitted) The video graphics array (VGA), as shown in Fig. 1, interfaces between video memory maps 0 - 3 and the controlling microprocessor. The VGA arbitrates requests for video memory that originate from both the microprocessor and the cathode ray tube controller (CRTC). The memory is organized as four maps to provide 4-way interleaving.