High-Speed ECL BIFET Receiver for High-End System
Original Publication Date: 1988-Jul-01
Included in the Prior Art Database: 2005-Feb-15
The BIFET process which mixes a CMOS and bipolar transistor on the same chip can be used for the design of receiver circuit with a better power performance factor of merit than the bipolar or the CMOS alone. The proposed BIFET receiver is based on a bipolar differential amplifier as input. It converts ECL levels used for OFF chip transmission in high-end systems to full CMOS levels used for logic or RAM circuits internal to a chip. The internal CMOS or BIFET circuits are fed through the maximum power supply from -2.2 V to +1.4 V, to have the maximum performance. The transmission of the data is made with a small signal swing defined positive and negative around the ground 0.0 V.