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Implementation of Binary Floating Point Architecture to Enable Efficient Emulation of Single and Double Precision Arithmetic

IP.com Disclosure Number: IPCOM000057938D
Original Publication Date: 1988-Aug-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Rodriquez, JR [+details]

Abstract

This article describes techniques for the implementation of a binary floating point (FP architecture based on the extended precision (XP) FP format defined by the IEEE 754 Standard on FP arithmetic that performs operations on single and double precision operands with performance that equals that of architectures that define single-precision (SP) and double-precision (DP) arithmetic). Implementations of this architecture will also emulate systems based on different architecture. This architecture defines all arithmetic operations to take place in the double extended format. Single or double precision operands must first be converted to double extended format, and the operation is executed in double extended format. The result of the operation is then converted to the precision of the result format.