Browse Prior Art Database

SELF-ALIGNED PROCESS for FABRICATING a REFRACTORY METAL GATE FIELD-EFFECT TRANSISTOR DEVICE

IP.com Disclosure Number: IPCOM000057943D
Original Publication Date: 1988-Aug-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Aboelfotoh, MO Krusin-Elbaum, L [+details]

Abstract

A self-aligned process for fabricating a refractory metal gate field-effect transistor (FET) is disclosed and comprised of: a) using deposition and etching techniques to provide metal gate portions on a silicon substrate comprised of a 100- to 250-angstrom layer of silicon oxide, a 2000- to 2500-angstrom layer of tungsten thereupon, followed by a 50- to 100-angstrom layer of silicon and a LPCVD deposited layer of silicon nitride; (Image Omitted) b) chemical vapor depositing a 500-angstrom layer of silicon oxide over the silicon substrate and gate portions and thereafter forming source and drain regions and a thin tungsten-silicide layer atop the gate portion by ion implantation and driving-in at elevated temperatures; c) chemical vapor depositing a 1000-angstrom layer of silicon oxide over the entire surface for self-alignment; d) RIE etching the silicon oxide layers until the silicon nitride layer is exposed, and removing the silicon nitride layer and cleaning the structure; e) magnetron sputtering a 300- to 500-angstrom layer of Ti-W alloy containing 30 to 50 atomic percent Ti over the entire surface of the structure; (Image Omitted) f) sintering the structure at elevated temperatures to cause excess Ti to form a homogeneous Ti silicide layer underneath an unreacted alloy layer; and g) etching only the unreacted alloy to leave Ti-silicide layers, which form ohmic contacts to shallow source and drain regions.