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Dynamic Arbitration Level Assignment for a Direct Memory Access Subsystem Disclosure Number: IPCOM000057946D
Original Publication Date: 1988-Aug-01
Included in the Prior Art Database: 2005-Feb-15

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Bealkowski, R Geisler, DR Macy, RB Zyvoloski, KM [+details]


This article describes a technique which allows hardware devices in a direct memory access (DMA) subsystem to be reconfigured to avoid conflicts and enhance performance criteria. In some personal computer (PC) systems which allow for devices to perform DMA transfers of data, each DMA device must have a priority level assigned in order to request the use of the PC bus. The priority level is referred to as the DMA arbitration level. Fig. 1 illustrates the DMA arbitration level environment. There are sixteen levels allowed for by the system. The hardware has direct support for eight arbitration levels. Each of those eight levels correspond to a priority. In the default case the priorities are 0-7, zero being the highest priority. Two of these default priority levels are reprogrammable to support a value in the range of 8-14.