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Interrupt Operation Detector for Intel 8273 Synchronous Data Link Control Protocol Controller Disclosure Number: IPCOM000057959D
Original Publication Date: 1988-Aug-01
Included in the Prior Art Database: 2005-Feb-15

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Lin, HC [+details]


This article describes a circuit arrangement which allows a multi- protocol communication (MPC) adapter to use an Intel* 8273 synchronous data link control (SDLC) protocol controller to perform data transfer in interrupt (INT) or direct memory access (DMA) mode. The multi-protocol communication (MPC) adapter has an Intel 8273 SDLC protocol controller to perform SDLC protocol communication. This controller can be programmed to do data transfer through either INT mode or DMA mode. In a personal computer having a multi-bus master architecture, the device requesting DMA service has to generate the '-preempt' signal. The '-preempt' signal of the MPC adapter will be active low by TxDRQ (Transmitter DMA request) or RxDRQ (Receiver DMA request) of the 8273 controller if it has been programmed to do data transfer in DMA mode.