Low End Parallel BUS Memory Refresh Activated BUS TIMEOUT Control
Original Publication Date: 1988-Aug-01
Included in the Prior Art Database: 2005-Feb-15
This article concerns a bus timeout circuit arrangement which is part of a central arbitration control point (CACP) container in a direct memory access (DMA) chip. The asynchronous low end parallel bus (LEPB) requires that bus masters relinquish the bus no later than 7.8 micro- seconds after preempt is driven low. The circuit described herein uses the system refresh request period to determine if a master has violated the 7.8 microsecond rule. It also protects dynamic memory data integrity by forcing a violating master off the bus, allowing memory refresh and reporting the fault to the system processor. The purpose of the bus timeout circuit disclosed herein is to identify and recover from severe errors resulting from illegal control of the system bus by a bus master.