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Operand Loading Sequencing for Floating Point Divide Chip

IP.com Disclosure Number: IPCOM000057976D
Original Publication Date: 1988-Aug-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Karim, FO [+details]

Abstract

This article describes a floating point unit design wherein the dividend register is loaded through a carry look ahead adder on one chip. Conventionally, two complementary metal oxide semi-conductor (CMOS) chips are used to perform many functions in the floating point unit, requiring a large amount of hardware in comparison to the size of the CMOS chip. In the design disclosed herein, the operands are sequence loaded which enables the use of one chip instead of two chips. Fig. 1 is a block diagram of the load sequencer. A data flow diagram for loading the operands is shown in Fig. 2. There are two sets of latches, each latch having only four cells. Each stage of the sequence directs the loading of the operands in 32 bits per stage.