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MATRIX REFLECTIONS and ROTATIONS for PROCESSOR ARRAYS

IP.com Disclosure Number: IPCOM000057984D
Original Publication Date: 1988-Aug-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Taylor, JL [+details]

Abstract

A fast processor array with bit slicing to implement matrix reflections and rotations is described. The matrix is bit sliced according to selected diagonal groupings and the bit slices reordered. The concepts may be used to process arrays of arbitrary large size. (Image Omitted) A known processor array shifts data using a NEWS (North East West South) network in which each element is connected to its four neighbors. A single shift (N, S, E, or W) may be executed at each cycle. At best, four unidirectional (N, S, E, and W) or two bidirectional (N-S, E-W) connections per element are needed, and only half the connections are used in any shift (since horizontal shifts do not use the vertical connections and vice-versa). This article has applications for the NEWS network (see Fig. 1).