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SELF-ALIGNED GATE PROCESS FOR GaAs GATE FET

IP.com Disclosure Number: IPCOM000058008D
Original Publication Date: 1988-Aug-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Baratte, H La Tulipe, DC [+details]

Abstract

A silicon dioxide mask can be used to separate source and drain metallurgy from gate metallurgy without the need of mask realignment in a single metal deposition step for a gallium arsenide gate field-effect transistor (FET) structure. The process produces a self-aligned structure and is shown in Figs. 1-3. Wafer 1, having barrier layer 2, of aluminum gallium arsenide and layer 3 n-type gallium arsenide is coated with a blanket deposition of silicon nitride 4 and tungsten silicide 5, shown in Fig. 1. The wafer is then patterned with photoresist in the desired stencil, and the tungsten silicide and silicon nitride are etched anisotropically down to layer 3.