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Hybrid Static Memory Cell

IP.com Disclosure Number: IPCOM000058011D
Original Publication Date: 1988-Aug-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Van Zeghbroeck, B [+details]

Abstract

Proposed is a static memory cell combining a semiconductor transistor with a Josephson junction and suitable for liquid nitrogen temperature operations. The Josephson junction serves to retain the information: a logic '0' when it is in the superconducting state, and a logic '1' when it is in the voltage state. The transistor is used to select a single cell in the array. Fig. 1 shows the simple circuit diagram of the cell. Source S and gate G of the field-effect transistor (FET) are connected to a bit- and a word-line of the memory array, whereas the drain electrode D is linked to the midpoint between the two serially-connected Josephson junctions J1 and J2; J1 serving as storage element, J2 being the load. The I-V characteristic of a single junction (J1) with another junction (J2) as load is shown in Fig. 2.